1. Field of the Invention
The present invention relates to a semiconductor memory, for example, a nonvolatile semiconductor memory such as a NOR flash memory.
2. Background Art
In recent years, various kinds of semiconductor memories (flash memories) have been developed which are made up of EEPROM cells and enable electrical writing and batch erasing. For example, a reading operation and a verifying operation of a NOR flash memory are performed by comparing, in a sense amplifier (differential amplifier circuit), currents passing through a selected memory cell and a reference cell (for example, see Japanese Patent Laid-Open No. 2007-42193).
In the reading operation of a semiconductor memory according to the prior art, a reading voltage is generated by, for example, a memory cell and the current source of the memory cell. Similarly, a reference voltage is generated by the reference cell and the current source of the reference cell. The sense amplifier is fed with these generated potentials as differential voltage inputs and outputs a signal corresponding to a comparison result. Based on the signal, data stored in the memory cell is obtained.
For a fast and stable operation of the sense amplifier, a large differential potential difference is desirable. For example, when a voltage required for a stable operation of the sense amplifier is represented as “V”, a time “t” for obtaining the potential difference is expressed by the following equation (1):t=CV/((Icell−Iload)−(Iref−Irload))  (1)where “C” represents the parasitic capacitance of a path from the current source on the side of the memory cell to the memory cell. In this design, an equivalent parasitic capacitance is provided for a path from the current source on the side of the reference cell to the reference cell. Further, a cell current is represented as “Icell”, a reference cell current (reference current) is represented as “Iref”, a supply current from the current source on the side of the memory cell is represented as “Iload”, and a supply current from the current source on the side of the reference cell is represented as “Irload”.
As expressed in equation (1), the time “t” gives a decision time of data stored in the memory cell, in the sense amplifier. Moreover, as semiconductor devices have been fabricated on smaller design rules in recent years, the wiring parasitic capacitance “C” tends to increase and the cell current tends to decrease. Particularly, in a semiconductor memory for storing multivalued data, a cell current difference further tends to decrease.
The tendency resulted from smaller design rules increases the reading time “t” as expressed in equation (1). In other words, in the prior art, when a semiconductor memory is fabricated on smaller design rules and is used for storing multivalued data, the reading time may increase.